Principal FPGA/Hardware Engineer

Description Looking for an opportunity to make an impact?

The Leidos Innovations Center has an immediate opening for a senior-level FPGA Engineer to work in San Diego, CA. This is an exciting opportunity to leverage your experience to develop and produce advanced satellite electronics, nuclear detection, radiography equipment, chemical and biological sensing instruments.

Emphasis is on research and development with activities ranging from support of early scientific research to transitioning products to production.

If this sounds like the kind of environment where you can thrive, keep reading!

The Challenge:

Complete ownership to architect the entire FPGA level design, develop/code/test the design, and finally integrate it on the hardware.

Lead a project team of 3-10 FPGA engineers.

Perform data analysis, write technical reports, ability of point of contact for the customer, perform internal and customer design reviews, write and maintain interface design documents for complex FPGA designs.

Develop and test FPGA designs for Chemical, Biological, Radiation, Nuclear, and Space sensor systems for federal government customers.

Develop and execute FPGA test plans, determine root cause of test failures, and iterate with senior staff to determine design changes to improve FPGA performance.

Support electrical engineering activities including FPGA designs and system integration and testing with CAD and lab activities.

Collaborate with a multi-disciplined design team to design and integrate DSP applications for latest System on a Chip (So

C) implementations such as Xilinx Zynq Ultrascale+ and Xilinx RFSo

C.

Understanding of image processing algorithms, basic knowledge of digital signal processing and tools to implement the DSP algorithms on the FPGA.

Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models.

Ensure designs synthesize, place and route, meeting timing requirements from high-speed FPGAs.

Analyze, design, simulate, and implement designs which interface to common signaling standards, typical IP hard macros such as SERDES, PLLS, etc. and/or protocols such PCIe, 10

GBE Ethernet, LVDS, etc.

Use judgment to perform technical troubleshooting and diagnosis of failed equipment and support root cause analysis.

What Sets You Apart:

Proven ability to architect the entire FPGA level design, develop/code/test the design, and finally integrate it on the hardware is a must for this position.

M.

S. degree in Electrical Engineering, Computer Engineering, or related field from an accredited college/university with 10+ years of relevant experience as an electrical engineer or computer engineer in an R&D environment.

Must be a U.

S Citizen and be able to obtain and maintain a Top Secret Security Clearance.

Experience or coursework related to testing FPGA or CPLD designs in an electronics lab.

Fluent in Vivado, Modelsim or Riviera. Fluent in testbenches and self-checking verification methods.

Working knowledge of electronics test equipment like function generators, oscilloscopes, logic analyzers, and lab power supplies.

Well-organized, reliable, attention to detail, demonstrated personal initiative. Ability to multi-task and prioritize workload. Good interpersonal skills and ability to coordinate work with others. Good oral and written communication skills.

Experience working with cross-functional R&D development teams.

Motivated self-starter able to work under minimal supervision and an entrepreneurial approach to roles and responsibilities.<20% travel to customer sites as required.

You’ll really WOW us having one or more of the following:

Masters’ degree or higher in Electrical/Computer Engineering with emphasis on digital/ASIC/FPGA design is a plus.

Breadth of experience in a complementary discipline ability to develop image processing algorithms in Matlab and implement them in HDL, FPGA design, or embedded software is a plus.

Experience reviewing and documenting technical data packages for military products.

Demonstrated mid or senior-level lead position in a large FPGA project.

Pay Range:

Pay Range $118,300.00 - $182,000.00 - $245,700.00

The Leidos pay range for this job level is a general guideline onlyand not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.